In general, when carrying out digital transmission of a video signal, in order to improve noise immunity performance, and to implement operating signalizing and reduce the number of signal lines, the digital video signal is transmitted after parallel-to-serial conversion is performed on the digital video signal. An IC (integrated circuit) used for the operating signalizing and parallel-to-serial conversion deals with (or covers) only the timing clock frequency range of standardized digital video signals, but cannot transmit any digital video signal whose frequency does not fall within this timing clock range because it is premised on transmission of such a digital video signal which is standardized beforehand, as in a case of, for example, VGA (Video Graphics Array).
On the other hand, there are various types of display units which display digital video signals, and in a case in which a display unit which receives a digital video signal whose frequency does not fall within the timing clock frequency range of standardized digital video signals and displays this digital video signal is used, a digital image transmission display device which has an IC which deals with only the timing clock frequency range of standardized digital video signals cannot carry out any image display using the display unit. In other words, any digital video signal whose frequency does not fall within the timing clock frequency range of standardized digital video signals cannot be transmitted to a display unit having a display area of a variant type whose frequency range does not fall within the timing clock frequency range of standardized digital video signals.
By the way, there has been proposed a digital image transmission apparatus which in order to prevent interference which is caused by an asynchronous operation of a 1-bit D/A circuit, multiplies the frequency of a horizontal synchronizing signal demultiplexed from a digital video signal so as to generate an operation clock, and in which a video signal control circuit digital-to-analog-converts various control data according to the operation clock and outputs them to a graphic processing circuit, and is reset in response to a vertical synchronizing signal demultiplexed from the digital video signal. The video signal control circuit is reset in response to the vertical synchronizing signal to prevent the asynchronous interference (for example, refer to patent reference 1).
Furthermore, there has been proposed a digital TV receiver which processes two or more television signals having different broadcasting formats, and which in order to prevent malfunctions due to use of an unsuitable clock or the like using a clock which is suitable for the format of a digital video signal, thereby providing a good image display which does not have any disorder, performs television signal processing on the inputted video signal using a processor, and selects, as a clock to be furnished to the processor, a clock which conforms to the broadcasting format of the inputted video signal (for example, refer to patent reference 2).
In addition, there has been proposed a digital image transmission apparatus which in order to display a digital image signal which is sent from a host computer on a dot-matrix display panel with display parameters, such as a dot clock frequency according to the type of the host computer, performs an A/D conversion and an interpolation process on the input image signal, demultiplexes a synchronizing signal from the input image signal to measure the period of the synchronizing signal, reads a corresponding display parameter from a table stored in a memory unit according to this measured value, controls an A/D converter, a digital image processing unit, etc. according to this display parameter, and outputs line display image data and a display address to control the display of the dot-matrix display panel using the digital image processing unit (for example, refer to patent reference 3).    [Patent reference 1] JP, 10-207442, A (see pp. 3 and 4, and FIGS. 1 to 3)    [Patent reference 2] JP, 10-215421, A (see pp. 5 and 6, and FIGS. 1 to 3)    [Patent reference 3] JP, 10-49103, A (see pp. 3 to 6, and FIGS. 1 to 7)
A problem with the prior art digital image transmission apparatus constructed as mentioned above and disclosed by patent reference 1 is that while the interference caused by asynchronous operation is prevented by resetting the video signal control circuit in response to the vertical synchronizing signal demultiplexed from the video signal, it cannot transmit any video signal whose frequency does not fall within the timing clock frequency range of standardized digital video signals to a display unit provided with a display area of a variant type whose frequency range does not fall within the timing clock frequency range of standardized digital video signals.
A problem with the prior art digital image transmission apparatus constructed as mentioned above and disclosed by patent reference 2 is that it only selects a clock which conforms to the broadcasting format of the inputted video signal as a clock which is to be furnished to the processor, and it cannot transmit any video signal whose frequency does not fall within the timing clock frequency range of standardized digital video signals to a display unit provided with a display area of a variant type whose frequency range does not fall within the timing clock frequency range of standardized digital video signals.
A problem with the prior art digital image transmission apparatus constructed as mentioned above and disclosed by patent reference 3 is that while it measures the period of the synchronizing signal, reads a corresponding display parameter from the table stored in the memory unit according to this measured value, controls the A/D converter, digital image processing unit, etc. according to this display parameter, it only selects the display parameter only according to the frequency of the synchronizing signal, and it cannot transmit any video signal whose frequency does not fall within the timing clock frequency range of standardized digital video signals to a display unit provided with a display area of a variant type whose frequency range does not fall within the timing clock frequency range of standardized digital video signals.
The present invention is made in order to solve the above-mentioned problems, and it is therefore an object of the present invention to provide a digital image transmission apparatus which can transmit a video signal whose frequency does not fall within the timing clock frequency range of standardized digital video signals to a display unit provided with a display area of a variant type whose frequency range does not fall within the timing clock frequency range of standardized digital video signals.